1. Field of the Invention
Embodiments of the present invention relate to semiconductor chip packages, and methods of manufacturing thereof. More particularly, embodiments of the present invention relate to wafer level chip packages and methods of manufacturing wafer level chip packages that are capable of providing improved protection against damage, e.g., during handling and/or subsequent wafer and/or chip processing, and reducing chipping and/or cracking defects.
2. Description of the Related Art
In general, semiconductor chip packages are provided to physically protect a semiconductor chip while establishing input and output connection portion(s) for connecting the semiconductor chip to other device(s). As electronic devices are becoming smaller and more complex, it is desirable to package a semiconductor chip as soon as possible after the semiconductor chip is formed to help protect the electronic devices of the semiconductor chip from damage that may occur during subsequent handling, etc. In some cases, the semiconductor chips of a wafer are first completely separated from the wafer before being packaged. In such cases, however, the semiconductor chips are susceptible to damage that may occur during the dicing process itself, i.e., process for separating the semiconductor chip(s) from the wafer.
Therefore, in some cases, wafer level packaging is employed to package the semiconductor chip(s) while the semiconductor chip(s) are still on the wafer. Wafer level packaging may offer many advantages, e.g., protection during dicing, relatively small, e.g., thinner, package size, relatively lighter package weight, and/or reduced manufacturing cost, etc. In general, conventional wafer level packages fail to cover all sides, e.g., all six sides, of a semiconductor chip, and/or conventional methods of wafer-level packaging semiconductor devices generally employ, e.g., multiple depositing steps and/or multiple planarization steps. Therefore, improved wafer level packages and simplified methods of packaging semiconductor chips at the wafer level are desired.